NAND NOR XOR XNOR

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity gates is

    Port ( inp1 : in  STD_LOGIC;

           inp2 : in  STD_LOGIC;

           op_nand : out  STD_LOGIC;

           op_nor : out  STD_LOGIC;

           op_xor : out  STD_LOGIC;

           op_xnor : out  STD_LOGIC);

end gates;

architecture Behavioral of gates is

begin

        process(inp1,inp2)

        begin

        op_nand <= inp1 nand inp2;

        op_nor <= inp1 nor inp2;

        op_xor <= inp1 xor inp2;

        op_xnor <= inp1 xnor inp2;

        end process;

end Behavioral;