Basic gates

HDL code for Basic Gates - AND OR & NOT

 

AND gate 

• in VHDL

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity and2 is                                              --entity declaration

    Port ( inp1 : in  STD_LOGIC;

           inp2 : in  STD_LOGIC;

           op : out  STD_LOGIC);

end and2;

architecture Behavioral of and2 is               --architecture part

begin

   process(inp1,inp2)

   begin

   op <= inp1 and inp2;

   end process;

end Behavioral;

•  in Verilog 

   

  module and2(op,inp1,inp2);
  output op;
  input inp1,inp2;
  assign op = inp1 & inp2;
  endmodule